1. Field of the Invention
The present invention relates to a liquid crystal display control device that executes an access control for a video memory storing image data for liquid crystal displaying.
2. Description of the Related Art
In general, a conventional liquid crystal display control device has a configuration as shown in FIG. 1. In FIG. 1, a CPU_I/F section 12 is a block for interfacing with a CPU 10, a memory control section 14 is a block for executing an access control for a VRAM (Video RAM) 16, the VRAM 16 is a memory for developing image data, a palette section 18 is a block for converting image data into color data for outputting to an LCD 24, an FRC (Frame Rate Control) section 20 is a block for performing a control of a flicker pattern for expressing halftones of a STN-type LCD, an LCD_I/F section 22 is a block for converting into a data format matching with a type of the LCD 24, and a control section 26 is a block for controlling the entire operation timing.
As shown in FIG. 2, there are two paths for accessing the VRAM 16. Specifically, one is (a) a path for the CPU 10 to write image data, and the other is (b) a path for the memory control section 14 to read display data. Inasmuch as access from the CPU 10 in the path (a) is performed at discretionary timing, there is a possibility that access in the path (a) and access in the path (b) occur simultaneously. In such an event, since data for screen displaying needs to be read at constant timing, it is necessary to give priority to the access in the path (b). At this time, as shown in a time chart of FIG. 3, WAIT is inserted with respect to the access in the path (a) until the access in the path (b) is finished. This mediating operation is implemented by the memory control section 14. Specifically, even if a data write request signal CPU_WR from the CPU 10 to the VRAM 16 is outputted, when there is a display data read request from the memory control section 14 (i.e. address signal LCD_ADD and data signal LCD_DAT are valid), data VRAM_DAT of the VRAM 16 is outputted to the palette section 18, and thus, until such an output is completed, WAIT is applied to the access from the CPU 10.
As described above, in the foregoing conventional access control, there has been a problem that since access from the LCD_I/F section 22 is given priority, access from the CPU 10 to the VRAM 16 is kept waiting while the memory control section 14 performs a display data read operation, so that the operation efficiency of the CPU 10 is lowered.